中文摘要：

基于OIF-VSR5—01．0规范，分析了12路并行40Gb／s甚短距离（VSR）光传输转换器模块的实现原理。采用top-down分析方法，使用硬件描述语言verilog，在可编程逻辑器件上完成了时钟数据恢复、基于字节对齐方案的帧同步、信道去斜移、比特间差奇偶校验（BIP）等功能模块的程序设计，实现了SFI-5与OIF-VSR5—01．0电信号格式的相互转换，并在Altera的Stratix Ⅱ GX系列的高速现场可编程门阵列（FPGA）上对功能模块进行了功能验证和联合仿真。结果表明所设计的各个功能模块满足系统应用要求，为下一步将系统设计转换为专用集成电路（ASIC）奠定了基础。

英文摘要：

The implementation principle of the signal converter of a 12-channel 40 Gb/s very short reach （VSR） parallel optical transmission system was analyzed according to the OIF-VSR5-01.0 agreement. Using the top-down analysis method and the hardware description language verilog, the modules of clock data recovery, byte alignment-based frame synchronism, channel alignment and bit interleaved parity （BIP） were designed on the programmable logic device, the signal transformation between the SFI-5 interface and the OIF-VSR5-01.0 interface was achieved, and the modules were verified and simulated on the high speed field programmable gate array （FPGA） of Altera StratixlI GX series. The simulation re- suits indicate that all the designed modules can meet the requirements of system application, which lay the fotmdation for application specific integrating circuits （ASIC）.