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中文摘要：
对基于现场可编程门阵列（FPGA）的全数字Costas环的设计方法进行了研究.首先,基于锁相环的模型,研究了数字Costas环的结构和性能,详尽的分析了数字Costas环的原理.然后,对数字Costas环的所有参数公式进行了准确细致的推导,对某些重要参数公式进行了修正,以提高所设计的数字Costas环的性能.最后,采用Ver-ilog HDL硬件描述语言,在Xilinx FPGA上开发了数字Costas环的各个模块,并综合成一个完整的Costas环.结合一个实际案例给出了实现后的数字Costas环的寄存器传输逻辑（RTL）原理图和仿真结果.仿真数据证明按照该设计方法和修正后的参数公式可以设计出实用的、性能十分优良的全数字Costas环.
英文摘要：
Design methods of the digital costas loop based on field programmable gate array（FPGA）was studied.First,the structure and performance of the digital costas loop based on the model of phase-locked loop was studied and a detailed analysis of the digital costas loop was presented.Then,all parameter formulas were derived accurately and some important formulas were modified in order to improve the performance of digital costas loop.Finally,each module of the costas loop was developed by Verilog HDL on a Xilinx FPGA,and all function blocks were assembled into a complete costas loop.Combined with an actual case,the register transfer logic（RTL） schematic of the digital costas loop which has been implemented on FPGA is displayed,and the simulation results are shown.The simulation data shows that the digital costas loop with practical and excellent performance can be achieved according to the design method and formulas presented by this paper.
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