中文摘要：

物理 unclonable 功能(PUF ) 在 IC 的生产期间使用控制不了的过程变化为每 IC 产生唯一的签名。它在象 FPGA 知识产权(IP ) 那样的安全有宽应用保护，关键产生和数字权利管理。戒指振荡器(RO ) PUF 和仲裁人 PUF 是最流行的 PUF，但是他们特殊没为 FPGA 被设计。当获得更少的挑战反应对时， RO PUF 招致高资源开销，并且要求“难宏”在 FPGA 上实现。仲裁人 PUF 带低资源开销，但是当它在 FPGA 上被印射时，它的结构有大偏爱。Anderson PUF 能探讨在 FPGA 上实现的当前的仲裁人和 RO PUF 的这些软弱。然而，它不能直接在新一代上被实现 28 nm FPGA。以便处理这些问题，这份报纸设计并且实现在 SLICEM 使用二 LUT 实现 PUF 的二个16位移动寄存器的基于延期的 PUF ，在carry 链到的 2-to-1 multiplexers 实现 PUF 的 multiplexers ，并且 8 个正反器到中的任何一个拴住1位的 PUF 签名。建议基于延期的 PUF 完全在 28 nm 广告 FPGA 上被认识到，并且试验性的结果显示出它的高唯一，可靠性和可配置性。而且，我们测试老化的影响上它，和建议 PUF 上的老化的效果是不足道的结果表演，与仅仅 6% 小点扭动。最后，在 FPGA 有约束力、不稳定的关键产生的建议 PUF 的前景被讨论。

英文摘要：

Physical unclonable function （PUF） makes use of the uncontrollable process variations during the production of IC to generate a unique signature for each IC. It has a wide application in security such as FPGA intellectual property （IP） protection, key generation and digital rights management. Ring oscillator （RO） PUF and Arbiter PUF are the most popular PUFs, but they are not specially designed for FPGA. RO PUF incurs high resource overhead while obtaining less challenge-response pairs, and requires ＂hard macros＂ to implement on FPGAs. The arbiter PUF brings low resource overhead, but its structure has big bias when it is mapped on FPGAs. Anderson PUF can address these weaknesses of current Arbiter and RO PUFs implemented on FPGAs. However, it cannot be directly implemented on the new generation 28 nm FPGAs. In order to address these problems, this paper designs and implements a delay-based PUF that uses two LUTs in an SLICEM to implement two 16-bit shift registers of the PUF, 2-to-1 multiplexers in the carry chain to implement the multiplexers of the PUF, and any one of the 8 flip-flops to latch 1-bit PUF signatures. The proposed delay-based PUF is completely realized on 28 nm commercial FPGAs, and the experimental results show its high uniqueness, reliability and reconfigurability. Moreover, we test the impact of aging on it, and the results show that the effect of aging on the proposed PUF is insignificant, with only 6% bit-flips. Finally, the prospects of the proposed PUF in the FPGA binding and volatile key generation are discussed.