欢迎您！东篱公司
退出
-
申报数据库
-
立项数据库
-
成果数据库
-
项目获奖数据库
中文摘要：
针对开关随输入信号幅度变化而导致的非线性,提出了一种基于栅压自举开关、带辅助电容的开环采样保持电路。电路采用双电容采样来消除电荷注入效应,并使用栅压自举开关代替传统双电容结构的输入开关,降低了输入开关的导通电阻,使得导通电阻与输入信号幅度无关,提高了电路的线性度。基于SMIC 0.18μm CMOS工艺的设计仿真结果表明,在电源电压为1.8V,输入信号频率为40 MHz,采样频率为500 MHz时,改进后的电路无杂散动态范围为92.49dB,信噪比为124.29dB,有效位数达14.98位。
英文摘要：
In order to improve the nonlinearity caused by switch changing with the input signal amplitude, an open-loop sam- ple and hold circuit based on a gate voltage bootstrapped switch with auxiliary capacitor is proposed. Double capacitance sampling method is adopted to eliminate the charge injection effect. And the input switch with traditional double capacitance structure is replaced by a grid bootstrapped switch, the input switch conduction resistance is effectively reduced, which makes conduction resistance independent of the input signal and improves the linearity of the circuit. The circuit is fabricated in SMIC 0.18 /~m CMOS process. Simulation results show that the improved circuit spurious-free-dynamic range is 92.49 dB, signal-to-noise ratio is 124.98 dB, the effective number of bit is 14.98 bit on the condition that 40 MHz input signal at 500 MHz sample frequency and 1.8 V supply voltage.
同期刊论文项目
同项目期刊论文
期刊信息
位置：