中文摘要：

针对LDPC码（Low Density Parity Check Codes）译码算法的特点和最新一代I mpulse C语言的并行编程技术,提出一种对LDPC码译码器进行FPGA（Field Programmable Gate Array）设计与实现的便捷新方案,以获得译码速率和硬件资源消耗的平衡.在XC2V2000芯片上实现了一种码率1/2,码长2500的（3,6）LDPC码译码器.实验表明当最大迭代次数为10次,主频50MHz时,译码速率可达10Mbps.

英文摘要：

In order to obtain the balance of the decoding rate and the hardware consumption,a new method to implement LDPC decoding algorithm is proposed.For the characteristics of the decoding algorithm,this method is based on an up-to-date parallel technique from Impulse C programming to hardware implementation.A decoder for a family of（3,6）LDPC Codes with a code rate of 0.5 and a block size of 2500 bits is implemented on Xilinx Virtex2 XC2V2000.By performing maximum 10 decoding iterations,the decoder can achieve a maximum bit throughput of 10Mbps.