中文摘要：

针对高性能浮点乘加部件中的应用需求，全定制设计了高性能52位或门和108位与门。设计中使用HSPICE工具进行电路模拟，模拟时使用CSM0．13ffm最慢工艺参数，电源电压为1．2V，温度为25℃。根据各种实现方式的电路特性，使用相应的理论上电路最大延时的输入激励进行模拟，输入激励的频率为1．25GHz，斜率为输入激励周期的10％。输出延时是每个输入周期中输入电压的50％到输出电压的50％之间的时间，最大延时是所有输入数据中的最长延时。根据不同的逻辑类型，设计实现了5种52位或门；选取了静态互补CMOS逻辑、np—CMOS逻辑两种直接实现的108位与门，并选取了多米诺逻辑间接实现方式。对比模拟结果可以得到，全定制设计实现的52位或门和108位与门在速度、功耗和面积方面都具有较优的综合性能。

英文摘要：

Because basic CMOS gates are widely employed in high-performance VLSI chips, we designed completely customized high performance 52bit or-gates and 108bit and-gates. HSPICE tools were used to simulate the circuits in a CSM 0.13 μm process, under 1.2 V power voltage at 25℃. Based on the features of different circuits, the corresponding input stimuli of the theoretically maximal delay were used for simulation. The frequency of the input stimulus was 1. 25 GHz, while the skew was set as 10% of the input stimulus cycle. The input delay was the interval from 50% of input voltage to 50% of output voltage per cycle, and the maximal delay was the maximum of the delays of all input data. According to the different logic types, five types of 52bit or-gates and two types of and-gates were designed. Comparing with the simulation results, we conclude that the fully customized gates we designed are superior in many aspects such as speed, power, and area.