中文摘要：

动态可重构高速串行总线（UM-BUS）是一种利用多通道并发冗余的方式来实现总线动态容错的高速串行总线。它的测试系统可以实现对总线的通信过程进行监测、存储与分析。由于测试系统需要在数据采集终端与PC之间建立高带宽的通信通道,设计了UM-BUS总线测试系统的PCIe2.0 x1通道的应用方案,设计并实现了基于FPGA的PCIe总线DMA数据传输方案。实验测试结果表明,实际传输速度可以稳定达到200 MB/s以上,完全满足总线测试系统中对数据传输速率的要求。

英文摘要：

Dynamically reconfigurable high- speed serial bus（ UM- BUS） is a novel high- speed serial bus with characteristics of dy-namic fault- tolerance and multi- channel concurrency and redundancy. Its test system can provide monitoring, storage and analysis for the communication process of UM- BUS. The test system requires a high- bandwidth communication channel between the data ac-quisition terminal with the PC. A PCIe2. 0 based solution for x1 channel is devised for the test system in this paper. Furthermore,Direct Memory Access（ DMA） data transfer has been successfully implemented based on PCIe bus on the FPGA platform. The ex-perimental results show that the actual data transfer speed can reach more than 200 MB / s. This design can fully satisfy the require-ments of data transfer rate for the test system.