中文摘要：

有非线性赔偿的一个高速度列平行 CDS/ADC 电路在这份报纸被建议。相关双采样(CDS ) 和 analog-to-digital 变换器(模数转换器) 工作基于二漂浮门 inverters 和开关电容器网络集成于一个三阶段的列平行电路。传统的单个斜坡的模数转换器的变换率被划分量子化到粗糙的步和好步加快。一个存储电容器被用来存储粗糙的步的结果并且定位好步的斜面信号的节，它能从 2 n 把钟步骤归结为 2 (n/2+1 ) 。漂浮的门 inverters 被实现减少电源消费。它的导致的非线性的偏移量被把一个赔偿模块介绍给 inverter 的输入取消，它能在建议电路的三个阶段使相等联合路径。这个电路与 640 为互补金属氧化物半导体图象传感器被设计并且模仿，

英文摘要：

A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper. The correlated double sampling （CDS） and analog-to-digital converter （ADC） functions are integrated in a threephase column-parallel circuit based on two floating gate inverters and switched-capacitor network. The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step. A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step, which can reduce the clock step from 2^n to 2^（n/2＋1）. The floating gate inverters are implemented to reduce the power consumption. Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter, which can equalize the coupling path in three phases of the proposed circuit. This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18 μm process. Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10 MHz. The power consumption of this circuit is less than 36.5 μW with a 3.3 V power supply. The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors.