中文摘要：

The design and test results of a 6-bit 3-Gsps analog-to-digital converter(ADC) using 1 m GaAs heterojunction bipolar transistor(HBT) technology are presented. The monolithic folding-interpolating ADC makes use of a track-and-hold amplifier(THA) with a highly linear input buffer to maintain a highly effective number of bits(ENOB). The ADC occupies an area of 4.32 × 3.66 mm2 and achieves 5.53 ENOB with an effective resolution bandwidth of 1.1 GHz at a sampling rate of 3 Gsps. The maximum DNL and INL are 0.36 LSB and 0.48 LSB,respectively.

英文摘要：

The design and test results of a 6-bit 3-Gsps analog-to-digital converter （ADC） using 1 μm GaAs het- erojunction bipolar transistor （HBT） technology are presented. The monolithic folding-interpolating ADC makes use of a track-and-hold amplifier （THA） with a highly linear input buffer to maintain a highly effective number of bits （ENOB）. The ADC occupies an area of 4.32 × 3.66 mm2 and achieves 5.53 ENOB with an effective resolution bandwidth of 1.l GHz at a sampling rate of 3 Gsps. The maximum DNL and INL are 0.36 LSB and 0.48 LSB, respectively.