中文摘要：

针对IEC61850标准所定义的过程总线上采样值高精度同步要求，提出一种基于弹性分组环（RPR）双环的数字化变电站秒脉冲（PPS）同步方案。在该方案中，RPR节点分为主、从2种节点。主节点接入源秒脉冲，从节点负责恢复PPS输出。PPS上升沿采用以太网物理层编码中的保留控制字K28．6表示．以抢占式高优先级（无延迟抖动）在RPR双环上同时传输：并采用主节点预补偿方式消除传输延迟的影响。对PPS恢复方案的误差进行了分析，给出了现场可编程门阵列（FPGA）的设计方法，采用硬件描述语言VerilogHDL设计，并用Modelsim软件做了仿真验证。结果表明：基于RPR双环的PPS恢复精度可以达到纳秒级：该方案使数字化变电站的过程总线和时钟同步网络合并成为可能。

英文摘要：

For the high-precision synchronization defined in IEC61850 for the data sampled on process bus,a PPS（Pulse Per Second） synchronization scheme based on RPR（Resilient Packet Ring） is proposed for digital substation. In this scheme,there are the master RPR node,which receives the PPS source,and the slave RPR node,which outputs the rebuilt PPS. The reserved control code K28.6 in Ethernet physical coding layer is used to represent the uprising edge of PPS,whieh is simultaneously transferred with the preemptive priority in both RPRs and a backoff algorithm is applied to balance out the propagation delay. The tolerance of PPS rebuilding is analyzed and the hardware design of FPGA（Field Programmable Gate Array） with Verilog HDL is introduced. The results of Modelsim-based simulation indicate that,the rebuilt PPS precision is up to nanosecond. The scheme makes it possible to merger the process bus and time synchronization network together in digital substation. This work is supported by the National Natural Science Foundation of China（NSFC）（50977012）.