中文摘要：

设计了一个适用于面阵CCD图像采集系统的10位、90MSPS流水线ADC.通过采用低功耗动态比较器和省略输入级采样/保持模块使得该高速ADC具有低功耗的优点.电路设计使用Charter0.35μm3.3V2P4M CMOS工艺.仿真结果表明：90MHz的采样速率、3.3MHz正弦信号输入下,该ADC模块具有9.3bit的有效分辨率,最大DNL为0.5LSB,最大INL为0.8LSB,整个ADC功耗仅为35.4mW.

英文摘要：

This paper presents design of a 10bit and 90 Ms/s pipeline ADC which is used in CCD image processor. Using Dynamic Comparator and omitting the input stage S/H （Sample and Hold）, the ADC achieved the characteristic of low-power dissipation. The designed ADC is implemented in Charter 0.35μm 2P4M CMOS process technology. Simulating results indicate that it can achieve an ENOB （Effective number of bit） of 9.3 bit, a maximum DNL of 0.5 LSB, a maximum INL of 0.8 LSB for a 3.3MHz sinusoid input at 90MHz sampling rate. The total power consumption of the ADC core is only 35.4mW from a 3.3V supply.