中文摘要：

介绍了一种TS201与FPGA通过高速链路口互联的方法,重点阐述了FPGA端收发模块的设计方案。该方案利用多级转换与状态机对模块结构进行了优化,并采用同步时钟与静态缓存有效解决了接收模块端链路时钟不连续的问题。仿真结果验证表明,设计的FPGA端收发模块,能实现符合链路口通信协议的数据传输。

英文摘要：

This paper studies the design and implementation of interconnection between TS201 DSP and FPGA. A scheme of FPGA node is proposed, which takes advantage of multilevel hierarchy and state machine to optimize the structure. In addition, a synchronous clock and static dual port syn- chronous RAMs are substituted for the discontinuous clock signal input at the receiver. Simulation results show that the FPGA node can ensure that the data transmission is in accordance with the LinkPort protocol.