中文摘要：

利用CMOS模拟电路设计了模拟概率计算模块，并以此为基础，通过晶体管级的模拟电路设计，构造了（5，2，3）网格码完整的新型模拟概率译码器，给出了模拟译码器的译码性能。当信噪比大于4．8dB时，对于950kHz的输入信号，输出没有错误。当输入信号为6MHz时，误码率约为10^-4。在5V工作条件下，译码器功耗为2．957mW。测试结果表明，在速度一定的条件下．与采用数字电路实现的译码器相比，该模拟译码器的功耗和芯片面积至少减少了一个数量级。该设计方法适用于实现网格码、Turbo码以及LDPC码等的模拟译码器。

英文摘要：

To study the design method of analog decoder, this paper realizes an analog probability computing module and fabricates a novel full analog probability decoder of （5, 2, 3） trellis code by CMOS circuits. The decoding performance of the analog decoder is given. When SNR is 4.8dBfor 950 kHz input signal, there is no error in the output of the decoder. When the frequency of the input signal is 6 MHz, the error bit rate is about 10^-4. Under work condition of 5 V, the power consumption of the decoder is 2. 957 mW. Simulation tests show that the analog decoder decreases at least one order of magnitude in power consumption and chip area at the same bit rate compared with the decoder designed by digital circuits. The design method can be used for fabricating the analog decoder of trellis code, Turbo code and low-density-pority-check （LDPC） code.