中文摘要：

The bufferless router emerges as an interesting option for cost-efficient in network-on-chip(NoC) design.However,the bufferless router only works well under low network load because deflection more easily occurs as the injection rate increases.In this paper,we propose a load balancing bufferless deflection router(LBBDR) for NoC that relieves the effect of deflection in bufferless NoC.The proposed LBBDR employs a balance toggle identifier in the source router to control the initial routing direction of X or Y for a flit in the network.Based on this mechanism,the flit is routed according to XY or YX routing in the network afterward.When two or more flits contend the same one desired output port a priority policy called nearer-first is used to address output ports allocation contention.Simulation results show that the proposed LBBDR yields an improvement of routing performance over the reported bufferless routing in the flit deflection rate,average packet latency and throughput by up to 13%,10%and 6%respectively.The layout area and power consumption compared with the reported schemes are 12%and7%less respectively.

英文摘要：

The bufferless router emerges as an interesting option for cost-efficient in network-on-chip （NoC） de- sign. However, the bufferless router only works well under low network load because deflection more easily occurs as the injection rate increases. In this paper, we propose a load balancing bufferless deflection router （LBBDR） for NoC that relieves the effect of deflection in bufferless NoC. The proposed LBBDR employs a balance toggle iden- tifier in the source router to control the initial routing direction of X or Y for a flit in the network. Based on this mechanism, the flit is routed according to XY or YX routing in the network afterward. When two or more flits con- tend the same one desired output port a priority policy called nearer-first is used to address output ports allocation contention. Simulation results show that the proposed LBBDR yields an improvement of routing performance over the reported bufferless routing in the flit deflection rate, average packet latency and throughput by up to 13%, 10% and 6% respectively. The layout area and power consumption compared with the reported schemes are 12% and 7% less respectively.