提出了一种针对高速中精度模数转换器的增益数模单元电路优化设计,满足8位80MS/s流水线模数转换器的要求.通过优化设计一种改进传输门开关,提高了增益数模单元电路的线性度;针对高增益两级宽带运算放大器,提出了一种宽带运算放大器优化设计方法,能有效地优化运算放大器的建立时间和功耗;优化设计了一种高速低功耗动态比较器,在提高速度方面具有优势.基于0.18μm 1.8V CMOS工艺完成了增益数模单元及8位80MS/s流水线模数转换器的流片验证,测试结果表明,在80MHz采样频率下,输入信号频率为35MHz时,模数转换器的信号噪声失调比为48.9dB,有效位数为7.83位.
A high speed and medium accuracy multiplying digital-to-analog converter(MDAC)circuit optimization design is presented for meeting the requirements of the 8bit,80MS/s pipelined analog-todigital(A/D)converter.An optimized transmission gate is adopted to improve the linearity of the MDAC circuit.In view of the high gain two-stage operational amplifier,design method in wideband operational amplifier design optimization is proposed and the settling time and power consumption of operational amplifier can be effectively decreased In addition,an improved high speed dynamic comparator is used in this design Fabricated in a 1.8V0.18μm CMOS process,this A/D converter with the proposed MDAC circuit achieves a signal to noise and distortion ratio(SNDR)of 54.6dB and an effective number of bits(ENOB)of 7.83 bit with a 35 MHz input signal at the 80 MHz sample rate.