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中文摘要：
An energy-efficient and highly linear capacitor switching procedure for successive approximation register（SAR） ADCs is presented.The proposed switching procedure achieves 37%less switching energy when compared to the well-known VCM-based switching scheme.Moreover,the proposed method shows better linearity than the VCM-based one.The proposed switching procedure is applied to a 10-bit 1.0 V 300 kS/s SAR ADC implemented in 0.18 μm standard CMOS.The measured results show the SAR ADC achieves an SNDR of 55.48 dB,SFDR of66.98 dB,and consumes 2.13 μW at a 1.0 V power supply,resulting in a figure-of-merit of 14.66 fJ/conversionstep.The measured peak DNL and INL are 0.52/-0.47 LSB and 0.72/-0.79 LSB,respectively,and the peak INL is observed at 1/4VFS and 3/4VFS.the same as the static nonlinearity model.
英文摘要：
An energy-efficient and highly linear capacitor switching procedure for successive approximation regis- ter （SAR） ADCs is presented. The proposed switching procedure achieves 37% less switching energy when compared to the well-known VcM-based switching scheme. Moreover, the proposed method shows better linearity than the VcM-based one. The proposed switching procedure is applied to a 10-bit 1.0 V 300 kS/s SAR ADC implemented in 0.18μm standard CMOS. The measured results show the SAR ADC achieves an SNDR of 55.48 dB, SFDR of 66.98 dB, and consumes 2.13 μW at a 1.0 V power supply, resulting in a figure-of-merit of 14.66 fJ/conversion- step. The measured peak DNL and 1NL are 0.52/-0.47 LSB and 0.72/-0.79 LSB, respectively, and the peak INL 1 is observed at 4^-1 VFS and 4^-3 VFS, the same as the static nonlinearity model.
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