提出了满足大整数相乘的CORDIC算法的改进措施,给出了改进后算法的VLSI结构及其VHDL代码的仿真时序,与理论计算结果相比较,修正后的CORDIC算法的大整数乘积运算结果与理论计算结果基本一致,可以满足数字系统设计中对大整数相乘设计要求。
To solve larger integer multiplication based on CORDIC,the improved measuring method of encoding Z-input on traditional CORDIC algorithm was proposed.The pipeline structure of this CORDIC algorithm and its VHDL code were elucidated.Simulation results were basically in agreement with theoretical value.The improvement on CORDIC algorithm is suitable for FPGA chips to run it.