中文摘要：

为了研究可控硅结构的静电释放保护器件结构尺寸与性能的关系,采用0.5μm的5 V/18 V CDMOS工艺流片两组SCR ESD器件,使用传输线脉冲测试系统测试器件的性能参数。实验结果表明,随着N阱内P＋区和P阱内N＋区间距从6μm增加到22μm,ESD器件的维持电压线性增大,从2.29 V升高到9.64 V,幅度达421%;单位面积的失效电流线性减小,幅度约为63%。分析与仿真结果表明,该线性关系具有普遍适用性,可用于调节器件的健壮性和功率耗散能力,满足智能功率集成电路的高压ESD防护需求。另一组随着P阱内P＋区和N＋区间距增大,维持电压和失效电流呈现非线性的变化,但触发电压迅速降低,可用于实现高压SCR ESD器件的低触发电压设计。

英文摘要：

Electrostatic discharge（ESD） properties of high voltage silicon controlled rectifier（HV-SCR） ESD devices can be adjusted by their key layout parameters. Two groups of HV-SCR ESD devices with particular layout parameters were fabricated in 0.5 μm 5 V/18 V CDMOS process, and their current-voltage curves, holding voltages, and failure currents were investigated and characterized by a transmission line pulse test system, respectively. Experimental data shows that with increasing layout spacing from P＋ implant in N well to N＋ implant in P well, the holding voltage grows linearly from 2.29 V to 9.64 V, as much as 421%, but the failure current per area decreases linearly about 63%. Using analysis and simulation results, two equations for the holding voltage and failure current were generalized properly. They can be used as a guideline to adjust ESD robustness and performance of HV- SCR ESD devices in smart power integrated circuits. However, with increasing layout spacing from P＋ implant to N＋ implant in P well, this phenomenon can＇t be found, but the trigger voltages of the devices decrease sharply, which can be used for low trigger voltage design of HV-SCR ESD devices.