中文摘要：

随着半导体工艺技术的发展，在单一芯片上集成多个处理器核已成为可能，在高端应用需求的驱动下，片上多处理器系统（Multi—Processor System-On-a-Chip，MPSoC）为高度并行的计算和通信提供了一种可行的解决方案。本文首先描述了一种基于AMBAAHB层次总线结构的片上多处理器系统硬件架构，然后以此为基础实现了2种并行化的JPEG解码算法。实验采用Altera Stratix Ⅱ FPGA器件，整个系统运行在60MHz的时钟频率下，与采用单个处理器实现的串行JPEG解码算法相比较，在集成了4个处理器核的MPSoC系统架构上实现的并行JPEG解码算法得到的最大加速比为2．23。

英文摘要：

With development of silicon technology,more than one processor is possible to integrate on a chip. In driving by the demands for high end applications, Multi-Processor System-On-a-Chip（MPSoC）provides a viable solution to highly parallel computations and communications. A kind of multi-processor hardware architecture based on hierarchical bus conforming to AMBA-AHB protocol is introduced in this paper,and then two algorithms for parallel JPEG decoding are presented under this framework. The whole system implemented with Altera Stratix II FPGA runs under the frequency of 60 MHz. Comparing with the serial JPEG decoding of single processor, the parallel one of four processors on this MPSoC system may obtain the maximum speedup of 2.23.