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中文摘要：
本文提出了一种应用于数据并行和高密度计算任务的新型动态可重构协处理器——DReAC.DReAC可以独立地以并行或流水工作模式重构协处理器内部数据路径,完成主处理器分配的任务.DReAC由全局控制器、计算阵列和阵列数据缓冲区三部分组成.文中简要介绍了DReAC系统模型,并使用该模型模拟了部份典型算法在DReAC中的实现.仿真结果表明,在典型的多媒体和信号处理应用中,DReAC能够达到通用处理器的10倍以上的速度,甚至在某些应用中远优于其他可重构处理器的性能.
英文摘要：
A new architecture for reconfigurable coprocessorr proposed, refers to as DReAC （ Dynamically Reconfigurable Array Coprocessor）, which is much helpful for the parallel data processing or the high density computation. DReAC consists of a recortfigurable computing array, a data-cache array and a global control unit. DRe, AC is able to work in parallel mode or pipeline mode. A behavioral model which was used in simulation algorithms was briefly introduced in this paper. The simulation results show that DReAC achieves much higher performance with 10x factor, comparing with traditional processors and some others reconfigurable processors.
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