中文摘要：

在40nIn工艺下完成了一款高性能DSP芯片中DDR3存储接口的物理设计，提出并实现了DDR3存储接口的布局规划、时钟树和时序收敛方法．在布局规划阶段，综合考虑了面积、时序等因素，确定了DDR3的布图形状大小以及内部宏单元、10单元的规划；在时序收敛阶段，分析了DDR3的时钟和路径结构，并针对关键路径进行精细的手工规划，提出并实现了自动化skew检查脚本框架，成功将各个PHY域内总线的偏差控制在40ps以内．实验结果表明，此设计达到了频率533MHz、最大数据率2133Mb／s的目标．

英文摘要：

In this paper, we finish the physical design of DDR3 memory interface in a high-performance DSP chip base on 40 nm process, and the floorplan, clock tree and timing convergence method of DDR3 memory interface are proposed and implemented. In the floorplan stage,the layout size of DDR3 and the planning of macros, IO units are determined considering the factors such as area and timing. In the timing convergence stage, we analyze the clock and path structure of DDR3, and make precise manual planning for the critical path. we also realized the automation skew check script,controll the bus skew within 40 ps. The experimental results show that the design of this paper achieves the goal of frequency 533 MHz, maximum data rate 2 133 Mb/s.