随着集成电路工艺水平的不断提升以及应用对处理器性能要求的日益增长,验证已成为未来片上多核处理器发展的主要技术瓶颈.文中深人分析了片上多核处理器验证中状态空间大、完备性不足、存储结构与互连网络验证复杂、硅后验证困难等突出问题,系统地总结了片上多核处理器模拟验证、硬件仿真、形式验证、硅后验证等方面的研究进展,并对该领域未来的发展方向进行了分析与展望.
With the rapid advancement of integrated circuits technology and the continuing increase of the application demand for performance, verification has become the main bottleneck of future on-chip multi-core processor. This paper analyzes deeply the challenging problems: large verification state space, difficulty in verification completeness, complicated memory structure and interconnection network, difficulty in post silicon verification. This paper also surveys the research progress in simulation, emulation, formal verification and post-silicon verification. Future research directions are also presented.