中文摘要：

研究了90nm工艺下栅氧化层厚度为1．4nm的n-MOSFET的击穿特性，包括V-ramp（斜坡电压）应力下器件栅电流模型和CVS（恒定电压应力）下的TDDB（经时击穿）特性，分析了电压应力下器件的失效和退化机理．发现器件的栅电流不是由单一的隧穿引起，同时还有电子的翻越和渗透．在电压应力下，SiO2中形成的缺陷不仅降低了SiO2的势垒高度，而且等效减小了SiO2的厚度（势垒宽度）．另外，每一个缺陷都会形成一个导电通道，这些导电通道的形成增大了栅电流，导致器件性能的退化，同时栅击穿时间变长．

英文摘要：

The characteristics of the TDDB （Time-dependent dielectric breakdown） under the CVS （constant voltage stress） and the gate current model of devices under V-ramp stress were studied in the 1.4nm-thick n-MOSFET. The degradation and failure mechanisms were analyzed. The gate current is produced by the tunneling, the electron surmounting and percolation. During the stress process, the created traps in the oxide not only debase the height of the SiO2 barrier, but also diminish the breadth of the barrier. Every trap engenders a conduction path. These paths enhance the gate current, degrade the device performance and prolong the broken-time of the gate oxide.