中文摘要：

针对二值逻辑电路连线多，且每根线携带的信息量少的弊端，研究了多元逻辑电路（DYL）基本门的内部结构和瞬态等效电路图。通过将瞬态等效电路打包并在Multisim软件平台上构建了DYL基本门器件及其等效电路，对DYL线性“与或”门的瞬态特性进行了分析与内部参数估算，同时给出了仿真分析。利用多值逻辑设计原理分析了器件逻辑真值表，采用数字系统分层次的设计方法，设计了DYL二值．四值开关电路。实验结果表明：DYL线性“与或”门固有延迟时间很小，更适合于高速电路的设计。逻辑门电路所实现的多值逻辑功能，大大减少了电路连线，节省了芯片面积。

英文摘要：

In view of the fact that the binary logic circuit has the defect of large amount of interconnecting lines and small information each line carries, the paper studied the multiple-valued logic circuit（DYL）and the inner structure of its basic gates and the equivalent circuit diagram of its transient state. An analysis of the transient characteristic and inner parameters estimation of the linear and-or gate was made by packing the equivalent circuit diagram of its transient state and constructing the basic gate devise and equivalent circuit diagram of DYL on the software platform of Multisim. And at the same time simulation analysis was also given. An analysis of the logic truth table of the device was made with the principle of multi-valued logic design. The DYL binary-four valued switched circuit was designed by the layered-design method of the digital system. The result of the experiment shows that the inherent delay time of the DYL linear and-or gate is very short and is more suitable for the design of high speed circuits. The logic gate circuit greatly reduces the amount of the interconnecting lines and therefore saves the chip area with its multiple-logic function.