中文摘要：

针对目前卷积码译码器占用资源较多,最高工作频率较低的缺点,设计了基于FPGA的（2,1,8）卷积码译码器。该译码器采用硬判决维特比译码算法。为有效提高译码器的工作频率,采用寄存器存储路径度量和幸存路径。通过分析译码启动过程中状态转移图上各个状态与其前一状态的关系,找到了硬件实现该过程的一种简单方法。通过分析译码过程中各个状态路径度量值之间的差值的变化规律,找到了采用硬判决维特比译码算法时,存储各个状态路径度量值的寄存器的最小位宽。在Quartus2集成开发平台上用Verilog HDL语言编写了译码器的源代码,并进行了编译、综合、仿真。结果表明所设计的卷积码译码器工作频率高,且输出时延小,占用资源较少。具有一定的实用价值。

英文摘要：

To overcome the defects of current convolutional code decoders in occupying too much resource and being with low working frequency,a new decoder of（2,1,8） convolutional code based on Viterbi algorithm is designed.To effectively improve the operating frequency of the decoder,registers are used to store the path metrics and survivor path of each state.By analyzing the relationship among one state and its former states which come to it,a simple way to realize the process in hardware is found.The minimum register width for storing the path metric of each state is calculated by analyzing the change rule of the path metric difference between any two states.The source code is written and then compiled,synthesized and simulated on the Quartus2 integrated development platform.The experimental results show that the decoder not only has a higher working frequency and shorter output delay,but also consumes less resource,and thus is of certain practical value.