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中文摘要：
设计了一种基于FPGA的高速双精度浮点乘法器．采用了基4Booth算法产生部分积，然后用优化的Wal—lace树阵列结构完成对部分积的累加得到伪和和伪进位，进而对伪和和伪进位采用了部分和并行相加得到最后尾数结果．采用了优化的5级流水线结构的设计在CycloneIIEP2C35F672C6器件上经过综合后运行频率可达123．32MHz．在同等优化下，相比于AlteraIP核在调用DSP乘法资源情况下运行速度提高大约11％，相比于不调用DSP乘法资源情况下运行速度提高大约67％．
英文摘要：
To considerably satisfy the requirement, a high speed double precision floating point multiplier based on FPGA is presented. The proposed design adopted radix-4 Booth coder to obtain partial products, then an optimal Wallace tree compression architecture is exploited on these partial products to get a pseudo-sum and pseudo-carry, which are partially accumulated in a parallel approach to generate mantissa of the product. The design with 5-stage pipeline architecture can achieve 123. 32MHz targeted at a Cyclone II EP2C35F672C6 device. By taking the same optimization efforts, the design gets 11% enhancement on operating frequency over an Altera IP core using DSP multipliers, while about 67% over such IP core without using DSP multipliers.
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