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中文摘要：
基于数字信号处理方法在粒子探测器信号处理中应用越来越广泛。论文基于“快通道＋慢通道”结合的方式设计了一个适于SOC设计的粒子探测器读出电路，并采用FPGA仿真平台对所设计的电路系统进行验证和初步测试。测试结果表明，数字处理器的快速通道和慢速通道能输出正确地梯形脉冲，峰值检测模块能正确地检测出脉冲的到达时间，堆积判弃，脉冲幅度提取电路正常；最终得到的等效噪声电荷为188e，总功耗为26mw，满足高精度低功耗粒子探测器读出电路设计要求。
英文摘要：
Method based on digital signal processing in particle detectors signal processing applications become increasingly widespread. A particle detector readout circuit based on ＂fast channel ＋ slow channel＂ method is given in the paper, which is good for SOC designs. Simulation scheme is also given to verify the correctness and accuracy of the circuit. The test results show that the digital processor outputs from both fast channel and slow channel are correct ; peak detector circuit can test the arrival time of pulse ; pile up rejecter and pulse attitude abstract circuit can both work; the ENC of the circuits designed is 188e; the power consumption is about 26roW. The circuit is suitable for high performance and low power dissipation applications.
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