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中文摘要：
现可用的同步电路综合工具对捆绑数据类异步电路直接映射的方法不能有效地约束时序，分模块综合的方法不能进行全局优化，其中以标准单元组成C单元降低了电路性能、增加了电路面积．通过将4相位捆绑数据寄存器流水线数据通道等效为一个同步流水线，可以自顶向下地进行有时序约束的综合，采用全定制C单元，并把其当作组合逻辑门进行分析，综合出的电路更加优化．使用此方法实现的一个数据流AES芯片的数据通道的面积延时积是直接映射方法的88％左右，实际芯片的整体性能优于一个由Balsa实现的AES芯片。
英文摘要：
The existing synchronous tools＇ direct mapping synthesis methods for bundled-data asynchronous circuit can＇t constrain timing effectively. The block by block synthesis can＇t achieve global optimization. Additionally, the standard-cells-composed C-elements decrease the performance and increase the size. Treated as a synchronous datapath, the 4 phase bundled-data pipeline can be compiled top-down and with timing constraints. The full-custom C-elements are used in it and regarded as combinatorial gates during timing analysis. Circuit synthesized using this methodology will be better. A data-flow AES chip was implemented with this method. Its datapath area-delay product is about 88 % of the result by direct mapping methods. The fabricated circuit＇s entire performance is higher than that of a Balsa-synthesized AES circuit.
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