中文摘要：

为解决测试图形生成电路功耗高、硬件开销大、故障检测难等问题,提出了一种用于内建自测试的低功耗测试图形生成方法。该方法将种子向量和SIC计数器生成向量进行运算,产生MSIC测试向量。通过设计一种可配置SIC计数器和种子生成电路,证明了该方法中任意的2个MSIC图形在任何情况下都是相异的。以国际基准测试电路ISCAS’89为对象,在nangate 45nm工艺上的仿真实验表明,基于该方法的测试生成电路的平均功耗占被测电路正常工作时平均功耗的1%～3%;与传统的伪随机测试生成电路相比,该测试生成电路的测试功耗降低了5.48%～66.86%,且其所生成的测试图形具有唯一性、低跳变等特性。

英文摘要：

A novel test pattern generation method for built-in-self-test（BIST） is proposed to solve the problems of power,hardware overhead and fault detection in VLSI test.The vectors generated by linear feedback shift register（LFSR） and single input change（SIC） counter are operated to generate multiple single-input change（MSIC） sequences.Then,a reconfigurable SIC counter and a test pattern generator are designed to verify the uniqueness of MSIC test patterns.Simulation results with ISCAS＇89 benchmarks based on the nangate 45 nm process show that the MSIC-TPG circuits impose about 1%-3% power overhead of the CUTs＇average working power.Comparisons with traditional pseudo random test patterns show that the test power decreases about 5.48%-66.86%,and that the test patterns generated by the proposed method have the advantages of uniqueness and minimum transitions.