中文摘要：

冗余二进制（RB）加法的进位无关特性和规整的压缩结构，可以设计高速冗余二进制乘法器。冗余二进制乘法器由RB部分积产生、RB部分积压缩树和RB-二进制数转换器三个关键模块构成。在此基于基-16 RB Booth编码结构提出了一种由进位跳跃加法器和并行前缀/进位选择混合加法器构成的冗余二进制-二进制数转换器。用Verilog HDL对该转换器进行描述，在Synopsys的VCS平台上进行仿真验证，在SMIC 45 nm的工艺下，通过Design Compiler 对转换器进行综合，比较普通的并行前缀/进位选择转换器，设计的64位转换器在延时、面积和功耗得到有效的改善。

英文摘要：

In this paper,a new RB-NB （redundant binary-normal binary） converter is proposed based on radix-16 RB Booth encoding structure,in which a hybrid of carry-skip adder and parallel-prefix/carry-select adder is used. The converter is realized by Verilog HDL and simulated in the VCS platform. Synthesis results using Artisan SMIC 45 nm standard-cell show that the proposed RB-NB converter achieves significant improvement in delay,area and power consumption,compared with the nor-mal parallel-prefix/carry-select converter.