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中文摘要：
设计了一个采用新型预充快速开启开关运放的低功耗12位40MS／s流水线模数转换器（ADC）。该转换器通过采用新型预充开关运放技术、采样保持电路消去结构、动态比较器和优化采样电容，大大降低了电路的功耗。电路设计采用1．8V1P6M0．18p．mCMOS工艺，仿真结果表明，在dOMS／s采样速率下，输入信号为19MHz时，无杂散动态范围（SFDR）为90．15dB，信噪失真比（SNDR）为72．98dB，功耗为27．9mw。
英文摘要：
This paper presents a 12-bit 40Msample/s low power pipelined analog-to-digital converter （ADC） with a novel pre- charged fast power-on switched operational amplifier. The converter＇ s low power consumption is realized by using the novel pre-charged fast power-on switched operational amplifier technique, the sample and hold amplifier （SHA）-less ar- chitecture, the dynamic comparator and the optimization of the sampling capacitor size. The ADC is designed in a 1.8V 1P6M 0.18pan CMOS process. The simulation results indicate that the ADC exhibits the spurious free dynamic range （SFDR） of 90.15dB, the signal to noise and distortion ratio （SNDR） of 72.98dB and a power consumption of 27.9mW when the frequency of its analog input signal is 19MHz.
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