中文摘要：

为了进一步提高集成电路互连寄生参数提取和电路时延分析的准确性，实现基于准确场求解器的线网寄生参数提取，提出一种快速、准确的集成电路版图数据转换方法．该方法读人二维GDSII版图数据和垂直工艺信息，基于一种扫描线算法判断导体块之间是否连接或重叠；然后利用链表、并查集等数据结构有效地描述三维互连结构及导体间连通关系，为后续电容提取和互连时延分析提供必要信息；最后输出电容提取场求解器所需的三维互连结构数据．基于实际版图的实验结果表明，文中方法比基于多边形两两判断的算法快4—7倍，且加速比随处理版图规模的增大而增大；该方法整体上具有O（nlog n）的时间复杂度，其中n为导体块数目，能够快速处理含1万块以上导体的大规模集成电路设计版图．

英文摘要：

In order to improve the accuracy of parasitic extraction and timing analysis of integrated circuits （ICs）, and perform the capacitance extraction with three-dimensional （3D） field solver, a fast transformation method is proposed to convert IC layout data. The method reads in GDSII file and vertical technology information, and then determines whether conductor blocks are connected or overlapped based on a sweep line algorithm. After that, the data structures of list and union-find set are used to describe the interconnect blocks and the connectivity among them, which is necessary for the subsequent capacitance extraction and timing analysis. Finally, the method outputs the 3D structure data for capacitance extraction field solver. The experimental results based on actual layouts show that, the proposed method is 4X-7X faster than the method based on pairwise analysis, and the speedup ratio increases as the number of blocks in the design increases. The time complexity of the proposed method is O（nlog n）, where n is the number of blocks in the design layout. Therefore, the method is able to handle actual circuit layout with more than 10,000 blocks efficiently.