中文摘要：

精确提取三维芯片中硅通孔（Through Silicon Via,TSV）电容在三维芯片设计中至关重要.使用后钻孔工艺（Via last technology）制造的TSV将贯穿导体层,使得TSV和互连线之间的耦合电容需要精确建模.文中提出的解析公式方法可以快速提取圆柱形TSV与互连线间的二维耦合电容.对于较短的互连线,文中采用基于最小二乘拟合得到的解析公式,而对于较长的互连线,使用基于电场模拟得到的解析公式.数值实验表明和商业软件Raphael相比,文中方法可以在结果误差不超过9.1％的情况下获得至少三千倍的加速.

英文摘要：

It is important to extract the parasitic parameters of through silicon vias （TSVs） for three-dimensional ICs （3-D ICs） design. TSVs in the via-last technology are fabricated through all the layers from the substrate to the topmost metal layer. Therefore, coupling capacitances between TSVs and interconnects should be accurately modeled. In this paper, an analytical method combining the least square fitting and field-based approach is proposed, to extract the 2-D coupling capacitance between actual cylindrical TSV and interconnection. Within this method, the least square fitting produces formulas for the short-interconnect structure, while the filed- based approach is used to extract the long-interconnect structure. Compared with the results obtained with the numerical field solver Raphael, the proposed method has more than several thousands of speedup with no more than 9.1% error.