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Circuit modeling and performance analysis of SWCNT bundle 3D interconnects
  • ISSN号：1674-4926
  • 期刊名称：Chinese Journal of Semiconductors
  • 时间：2013.9
  • 页码：095014-1-095014-7
  • 分类：TP393[自动化与计算机技术—计算机应用技术;自动化与计算机技术—计算机科学与技术] O613.71[理学—无机化学;理学—化学]
  • 作者机构：[1]Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University,Xi'an 710071, China
  • 相关基金：supported by the National Natural Science Foundation of China(Nos.61234002,61006028,61204044);the National High-Tech Program of China(Nos.2012AA012302,2013AA011203)
  • 相关项目：三维集成电路的TSV模型及热管理技术研究
作者： Libo Qian|Zhangming Zhu|Ruixue Ding|Yintang Yang|
关键词： 单壁碳纳米管束, 集成电路, 性能分析, 互连, 3D, 建模, 信号延迟, 铜导线, three-dimensional integrated circuits （3D ICs）, carbon nanotube （CNT）, signal delay, repeater inser-tion
中文摘要：

Metallic carbon nanotubes(CNTs) have been proposed as a promising alternative to Cu interconnects in future integrated circuits(ICs) for their remarkable conductive, mechanical and thermal properties. Compact equivalent circuit models for single-walled carbon nanotube(SWCNT) bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional(3D) ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respectively.

英文摘要：

Metallic carbon nanotubes （CNTs） have been proposed as a promising alternative to Cu interconnects in future integrated circuits （ICs） for their remarkable conductive, mechanical and thermal properties. Compact equiv alent circuit models for single-walled carbon nanotube （SWCNT） bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional （3D） ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respec tively.

同期刊论文项目
纳米级超低功耗CMOS集成电路与SoC技术研究
期刊论文 38
三维集成电路的TSV模型及热管理技术研究
期刊论文 21
CMOS数据转换器关键器件匹配性及高层次模型研究
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期刊信息
  • 《半导体学报：英文版》
  • 中国科技核心期刊
  • 主管单位:中国科学院
  • 主办单位:中国电子学会 中国科学院半导体研究所
  • 主编：李树深
  • 地址：北京912信箱
  • 邮编：100083
  • 邮箱：cjs@semi.ac.cn
  • 电话：010-82304277
  • 国际标准刊号：ISSN：1674-4926
  • 国内统一刊号：ISSN：11-5781/TN
  • 邮发代号:2-184
  • 获奖情况:
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  • 被引量:7754