通过对流水线ADC的误差源的分析,提出了一种使用于高精度流水线ADC的后台校准算法.这种方法改进模拟电路结构以实现后台的多次采样,消除了前级电容失配的增益误差及各级的热噪声等随机模式误差.在SMIC 0.18μm工艺下实现了一个3M/s 12位每级1.5位的带有校准的流水线ADC,使用Cadence工具仿真得出该电路在3.3V电压下直流功耗55mW,版图面积0.52mm2,加入校准后增加的面积约为5%.校准算法使流水线ADC的SNR由50.3dB上升到68.5dB,ENOB由8.1上升到11.1.
A new background calibration method us presented used in high precision pipeline ADC.With analyzing the error sources,the calibration improves the analog circuit to achieve multiple sampling,which eliminates the gain error caused by capacitance mismatch in front stages and random pattern noise caused by thermal noise in all stages.A differential 3M/s.12-bit,1.5bit per stage pipeline ADC with calibration is designed and verified in SMIC 0.18μm CMOS process.The circuit with typical supply voltage 3.3Vconsumes 55mW power dissipation and occupies 0.52mm2 die area,only about 5%increase for calibration.The measured SNRis improved from50.3dBto68.5dBandENOBisincreasedfrom8.1to11.1.