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中文摘要：
基于chartered 0.35μm工艺，采用PMOS管作为输入管的折叠式共源共栅结构，设计了一种采用增益提高技术的两级运算放大器。利用Cadence公司的spectre对电路进行仿真，该电路在3.3V电源电压下具有125．8dB的直流开环增益，2．43MHz的单位增益带宽，61.2°的相位裕度，96.3dB的共模抑制比。
英文摘要：
Based on Chartered 0.35 μm process, a two-stage operational amplifier with gain boosting technology was designed by using the PMOS transistor as the folded-cascode structure of the input tube. The circuit was simulated by Spectre made in Cadence. The circuit at 3.3 V has DC open-loop gain of 125.8 dB, unity-gain bandwidth of 2.43 MHz, phase margin of 61.2°, CMRR of 96.3 dB.
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Leakage current, active power, and delay analysis of dynamic dual V-t CMOS circuits under P-V-T fluc
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