中文摘要：

作为技术往下移到纳米规模的半导体，漏电源成为了全部的电源消费的一个重要部件。在这份报纸，我们在场安排算法完成与环为应用程序节省很长的指令词(VLIW ) 体系结构的漏精力的漏知道的模。建议算法被设计最大化与双阀值的牙齿逻辑综合的功能单位的懒散，并且减少转变在之间的数字活跃并且睡觉模式。我们在三个船体并列的游艇编译器实现了我们的技术并且在三个船体并列的游艇的周期精确的 VLIW 模拟器上从 DSPstone 和 Mibench 用一套嵌入的基准进行了实验。结果证明我们的技术完成重要的漏精力节省与相比一以前出版了基于 DAG (指导的非循环的图) 漏知道的安排算法。

英文摘要：

As semi-conductor technologies move down to the nanometer scale, leakage power has become a significant component of the total power consumption. In this paper, we present a leakage-aware modulo scheduling algorithm to achieve leakage energy saving for applications with loops on Very Long Instruction Word （VLIW） architectures. The proposed algorithm is designed to maximize the idleness of function units integrated with the dual-threshold domino logic, and reduce the number of transitions between the active and sleep modes. We have implemented our technique in the Trimaran compiler and conducted experiments using a set of embedded benchmarks from DSPstone and Mibench on the cycle-accurate VLIW simulator of Trimaran. The results show that our technique achieves significant leakage energy saving compared with a previously published DAG-based （Directed Acyclic Graph） leakage-aware scheduling algorithm.