使用冗余行覆盖占故障总数70%的单故障,导致冗余资源的浪费.为提高冗余资源的利用率,提出一种高效的修复方案,即冗余行覆盖多故障,纠错码修复单故障.当采用码率大于1/2的纠错码修复单故障时,校验位的长度小于冗余行的长度,节约了面积开销.通过2^4×8比特静态随机存取存储器(SRAM)的自修复实验,验证了新方案的可行性.实验结果表明,与冗余行结构相比。新的修复方案可以减小面积开销,提高芯片的最大工作频率.
The use of redundant rows for covering single cell faults, which possessed about 70% of the total faults, leaded to the waste of redundant resources. In order to improve utilization rate, an integrated ECC and redundancy repair scheme is proposed. In the proposed scheme, the redundancy repair and ECC techniques are used to correct multiple and single word faults. If the code rate ( i. e. , the ratio of the length of information bits to code length) is lager than 1/2, ECC uses less area overhead to repair single word faults than redundant rows. The feasibility of the proposed scheme is justified on a 2^4×8-b SRAM. Experimental results demonstrate that both area overhead and maximum frequency are improved by the new approach.