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中文摘要：
提出了一种基于真值表变量分离技术的数字电路进化设计方法.该方法旨在减少待进化系统的输入输出位数,将较难实现的整体进化系统分解成几个容易实现的进化子系统,从而实现较大规模数字电路的进化设计.同时结合多目标遗传算法,优化电路结构.并以加法器和乘法器为设计实例,结果证明了该方法能有效进化出较大规模的数字电路,得到的进化电路资源更少,时延更短.
英文摘要：
Aiming at the scalability issue of evolvable hardware,partitioning truth table variable technique for digital circuit evolution is introduced.The method is to reduce the digits of inputs and outputs of the evolved system,that is to divide the intact target system which is evolved difficultly into several sub-systems which are evolved easily to evolve larger digital circuit.At the same time,multi-objective genetic algorithm is combined to optimize some parts of the circuit.Adder and Multiplier circuits are taken as examples.The experimental results prove that,by employing the proposed scheme,digital circuits can be designed with less resources and time delay more effectively in larger scale.
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