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中文摘要：
To enhance the robustness of LDMOS ESD protection devices,the influence of a source-bulk layout structure is analyzed by theoretical analysis and numerical simulation.Novel structures with varied source-bulk layout structures are fabricated and compared.As demonstrated by TLP testing,the optimized structure has an 88% larger It2 than a conventional one,and its Vt1 is reduced from 55.53 to 50.69 V.
英文摘要：
To enhance the robustness of LDMOS ESD protection devices, the influence of a source-bulk layout structure is analyzed by theoretical analysis and numerical simulation. Novel structures with varied source-bulk layout structures are fabricated and compared. As demonstrated by TLP testing, the optimized structure has an 88% larger It2 than a conventional one, and its Vtl is reduced from 55.53 to 50.69 V.
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