位置：成果数据库 > 会议 > 会议详情页
Pub/Sub on stream: A multi-core based message broker with QoS support
  • 所属机构名称：清华大学
  • 会议名称：6th ACM International Conference on Distributed Event-Based Systems, DEBS';12
  • 成果类型：会议
  • 相关项目：三维多核片上系统的体系结构和设计研究
作者： Wang, Zhaoran1|Zhang, Yu2|Chang, Xiaotao1|Mi, Xiang1|Wang, Yu1|Wang, Kun2|Yang, Huazhong1|
同会议论文项目
三维多核片上系统的体系结构和设计研究
期刊论文 32 会议论文 64
同项目会议论文
Thermal-aware power network design for IR drop reduction in 3D ICs
Bandwidth-aware reconfigurable cache design with hybrid memory technologies
Moguls: A model to explore the memory hierarchy for bandwidth improvements
A compression-based area-efficient recovery architecture for nonvolatile processors
Parallel circuit simulation on multi/many-core systems
Code-independent output impedance: A new approach to increasing the linearity of current-steering DA
An informed unipolar spread spectrum modulation for self-synchronized robust watermarking
An energy-efficient 3D CMP design with fine-grained voltage scaling
On-Chip Hybrid Power Supply System for Wireless Sensor Nodes
Low power memristor-based ReRAM design with error correcting code
Design trade-offs for high density cross-point resistive memory
A low latency variance NoC router
AdaMS: Adaptive MLC/SLC phase-change memory design for file storage
Moguls: A model to explore the memory hierarchy for bandwidth improvements
Device-architecture co-optimization of STT-RAM based memory for low power embedded systems
Leveraging on-chip DRAM stacking in an embedded 3D multi-core DSP system
Sparse LU factorization for parallel circuit simulation on GPU
Robust and transparent audio watermarking based on improved spread spectrum and psychoacoustic maski
A low-power all-digital GFSK demodulator with robust clock data recovery
3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs
Point and discard: A hard-error-tolerant architecture for non-volatile last level caches
Application specific sensor node architecture optimization - Experiences from field deployments
Energy-efficient GPU design with reconfigurable in-package graphics memory
A PVT-aware and low power pulse-triggered flip-flop
A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops
An adaptive LU factorization algorithm for parallel circuit simulation
PDPR: Fine-grained placement for dynamic partially reconfigurable FPGAs
PS3-RAM: A fast portable and scalable statistical STT-RAM reliability analysis method
Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs
Mitigating electromigration of power supply networks using bidirectional current stress
Automated mapping for reconfigurable single-electron transistor arrays
An energy harvesting nonvolatile sensor node and its application to distributed moving object detect
Design methodology of multistage time-domain logic speculation circuits
System-level design space exploration for three-dimensional (3D) SoCs
A hardware-software collaborated method for soft-error tolerant MPSoC
A heterogeneous accelerator platform for multi-subject voxel-based brain network analysis
The impact of correlation between NBTI and TDDB on the performance of digital circuits
Circuit-level delay modeling considering both TDDB and NBTI
Yield-aware time-efficient testing and self-fixing design for TSV-based 3D ICs
A low-power fast-settling bond-wire frequency synthesizer with a dynamic-bandwidth scheme
Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs
Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory
An efficient methodology for transaction-level design of multi-core h.264 video decoder
System-level evaluation of video processing system using simplescalar-based multi-core processor sim
Design and implementation of a hybrid sensor network for Milu Deer monitoring
Energy-efficient multi-level cell phase-change memory system with data encoding
Gemma in April: A matrix-like parallel programming architecture on OpenCL
FPGA accelerated parallel sparse matrix factorization for circuit simulations
Enabling architectural innovations using non-volatile memory
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
A hierarchical C2RTL framework for FIFO-connected stream applications
Probabilistic brain fiber tractography on GPUs
Modeling and design exploration of FBDRAM as on-chip memory
NVMain: An architectural-level main memory simulator for emerging non-volatile memories
Low-power off-chip memory design for video decoder using embedded bus-invert coding
Temporal performance degradation under RTN: Evaluation and mitigation for nanoscale circuits
Impact of circuit degradation on FPGA design security
Enabling quality-of-service in nanophotonic network-on-chip
MorphCache: A reconfigurable adaptive multi-level cache hierarchy
A low-power IF circuit with 5 -dB minimum input SNR for GFSK low-IF receivers
A reconfigurable computing approach for efficient and scalable parallel graph exploration
A frequent-value based PRAM memory architecture
Design implications of memristor-based RRAM cross-point structures