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三维多核片上系统的体系结构和设计研究
  • 项目名称：三维多核片上系统的体系结构和设计研究
  • 项目类别：海外及港澳学者合作研究基金
  • 批准号：61028006
  • 申请代码：F0203
  • 项目来源：国家自然科学基金
  • 研究期限：2011-01-01-2012-12-31
  • 项目负责人：谢源
  • 负责人职称：教授
  • 依托单位：清华大学
  • 批准年度：2010
中文摘要：

在计算机体系结构，电子系统设计自动化，嵌入式系统，低功耗电路与系统，新型存储技术及应用等方面取得了多项开创性成果，尤其在三维集成电路设计，EDA，体系结构上有突出的贡献，为该领域世界著名专家。在著名的国际期刊和著名的国际学术会议（包括三大计算机体系结构大会和四大EDA会议）共发表近130篇论文。出版英文专著1本（第一本关于三维集成电路设计和体系结构的书）。2006年获得美国国家自然科学基金会Faculty Career Award，2006年入选中国教育部春晖计划，2008年获得IBM Faculty Award，2009年入选中国国家自然科学基金会的"龙星计划"，2010年成为ACM Distinguished Speaker。担任5个IEEE/ACM/IET国际期刊的Associate Editor，10多个国际会议的程序委员会委员，以及两个大会的程序委员会主席。

中文主题词： 3D IC；体系结构；EDA tools；数/模混合IC；
英文摘要：

3D IC；architecuture；EDA tools；digital/analog mixed-signal IC；

英文主题词： 3D IC；architecuture；EDA tools；digital/analog mixed-signal IC；
结论摘要：

作为继续遵循“摩尔定律”的有效方法之一，三维集成电路（3D IC）通过多层的堆叠和垂直互连（例如TSV）不仅能够有效的缩减片上互连线长度、增加单位面积的片上集成度，而且可以低成本的实现不同工艺的异构集成。相比与传统2D 芯片设计方式，新的设计维度增加了芯片设计空间的复杂度，面临着如下关键问题1）需要基于应用的新体系结构级设计空间探索和评估方法；2）缺乏支撑三维集成设计的EDA环境及设计方法；3）需要解决三维堆叠下芯片面临的诸多可靠性问题，例如热、应力等；4）缺乏针对三维集成芯片的可测性设计和测试方法。针对以上分析，本项目旨在开展的相应研究包括3D MPSoC的体系结构评估和设计； 基于现有的2D的设计流程，设计一套实用的3D MPSoC设计流程，解决三维芯片中的支持系统（时钟和电源问题）和可测性问题；研究基于应用的3D MPSoC设计方法。 首先，为了探索3D MPSoC的新型体系结构和设计方法，本项目从三维堆叠的通信和存储架构方面展开深入研究，分别研究了在现有多核处理器平台上堆叠常规存储器（DRAM等）和非易失性存储器（STT-RAM、RRAM等）的新型结构和设计方法，其中我们提出的基于RRAM的交叉点结构已得到学术和工业界广泛认可和采用（两年间已经被引用15次）。其次，本项目还从完善现有3D MPSoC设计流程着手，结合考虑3D MPSoC面临的热、老化、可测性等关键问题，开发了用于快速仿真（被引用5次）、时钟树综合、自动布局布图（被引用5次）等EDA工具，对三维集成电路的广泛推广具有重要作用。另外，本项目还针对无线传感器节点应用验证了三维集成电路的高集成密度、小体积和异构集成等特点。我们首次提出了三维片上混合电源系统结构和电源管理算法，能延长无线传感器节点2-4倍的使用寿命。针对无线传感器节点芯片的关键组成部分——模数转换器（ADC）， 我们设计了一种更加节能的两层堆叠三维ADC芯片，相比传统2D设计节省25%的功耗，并提出了三维数模混合芯片的低成本、有效的设计方法和仿真方法。 两年间完成了原计划的研究内容，基于在三维集成电路新型体系结构探索、三维集成电路设计EDA支撑工具开发、三维集成电路可靠性及可测性设计等诸多方面的深入研究成果，充分得到了学术和工业界的认可，为三维集成电路的应用推广起到重要作用。

成果综合统计
成果类型
数量
  • 期刊论文
  • 会议论文
  • 专利
  • 获奖
  • 著作
  • 32
  • 64
  • 0
  • 0
  • 0
期刊论文
Modeling, Architecture, and Applications for Emerging Memory Technologies
An FPGA-Based Accelerator for LambdaRank in Web Search Engines
Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation
Power analysis attack resistance engineering by dynamic voltage and frequency scaling
Balanced Switching Schemes for Gradient-Error Compensation in Current-Steering DACs
Parametric yield-driven resource binding in high-level synthesis with multi-Vth/Vdd library and devi
ESL design methodology
Distributed Smart Camera Network
Soft error rate analysis for combinational logic using an accurate electrical masking model
Influence of node dynamics on cluster global time continuity
Three-dimensional integrated circuits: Design, EDA, and architecture
Hybrid Checkpointing Using Emerging Nonvolatile Memories for Future Exascale Systems
Variation-aware task and communication mapping for MPSoC architecture
New development of analog-to-digital converters
Exploiting heterogeneity for energy efficiency in chip multiprocessors
A robust and simple two-mode digital calibration technique for pipelined ADC
Editorial: Three-dimensional integrated circuits design
A Low-Power IF Circuit with 5 dB Minimum Input SNR for GFSK Low-IF Receivers
A PLL based WSN transmitter and I/Q LO signal generator at 430-435 MHz
An Energy Efficient Sensor Network Processor with Latency-Aware Adaptive Compression
Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI: Foreword
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory
Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs
Selective Host-Interference Cancellation: A New Informed Embedding Strategy for Spread Spectrum Wate
Design and implementation of motion compensator in memory reduced HDTV decoder with embedded compres
A 12-bit self-calibrating SAR ADC achieving a Nyquist 90.4-dB SFDR
Performance/Thermal-Aware Design of 3D-Stacked L2 Caches for CMPs
会议论文
Thermal-aware power network design for IR drop reduction in 3D ICs
Bandwidth-aware reconfigurable cache design with hybrid memory technologies
Moguls: A model to explore the memory hierarchy for bandwidth improvements
A compression-based area-efficient recovery architecture for nonvolatile processors
Parallel circuit simulation on multi/many-core systems
Code-independent output impedance: A new approach to increasing the linearity of current-steering DA
Pub/Sub on stream: A multi-core based message broker with QoS support
An informed unipolar spread spectrum modulation for self-synchronized robust watermarking
An energy-efficient 3D CMP design with fine-grained voltage scaling
On-Chip Hybrid Power Supply System for Wireless Sensor Nodes
Low power memristor-based ReRAM design with error correcting code
Design trade-offs for high density cross-point resistive memory
A low latency variance NoC router
AdaMS: Adaptive MLC/SLC phase-change memory design for file storage
Moguls: A model to explore the memory hierarchy for bandwidth improvements
Device-architecture co-optimization of STT-RAM based memory for low power embedded systems
Leveraging on-chip DRAM stacking in an embedded 3D multi-core DSP system
Sparse LU factorization for parallel circuit simulation on GPU
Robust and transparent audio watermarking based on improved spread spectrum and psychoacoustic maski
A low-power all-digital GFSK demodulator with robust clock data recovery
3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs
Point and discard: A hard-error-tolerant architecture for non-volatile last level caches
Application specific sensor node architecture optimization - Experiences from field deployments
Energy-efficient GPU design with reconfigurable in-package graphics memory
A PVT-aware and low power pulse-triggered flip-flop
A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops
An adaptive LU factorization algorithm for parallel circuit simulation
PDPR: Fine-grained placement for dynamic partially reconfigurable FPGAs
PS3-RAM: A fast portable and scalable statistical STT-RAM reliability analysis method
Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs
Mitigating electromigration of power supply networks using bidirectional current stress
Automated mapping for reconfigurable single-electron transistor arrays
An energy harvesting nonvolatile sensor node and its application to distributed moving object detect
Design methodology of multistage time-domain logic speculation circuits
System-level design space exploration for three-dimensional (3D) SoCs
A hardware-software collaborated method for soft-error tolerant MPSoC
A heterogeneous accelerator platform for multi-subject voxel-based brain network analysis
The impact of correlation between NBTI and TDDB on the performance of digital circuits
Circuit-level delay modeling considering both TDDB and NBTI
Yield-aware time-efficient testing and self-fixing design for TSV-based 3D ICs
A low-power fast-settling bond-wire frequency synthesizer with a dynamic-bandwidth scheme
Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs
Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory
An efficient methodology for transaction-level design of multi-core h.264 video decoder
System-level evaluation of video processing system using simplescalar-based multi-core processor sim
Design and implementation of a hybrid sensor network for Milu Deer monitoring
Energy-efficient multi-level cell phase-change memory system with data encoding
Gemma in April: A matrix-like parallel programming architecture on OpenCL
FPGA accelerated parallel sparse matrix factorization for circuit simulations
Enabling architectural innovations using non-volatile memory
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
A hierarchical C2RTL framework for FIFO-connected stream applications
Probabilistic brain fiber tractography on GPUs
Modeling and design exploration of FBDRAM as on-chip memory
NVMain: An architectural-level main memory simulator for emerging non-volatile memories
Low-power off-chip memory design for video decoder using embedded bus-invert coding
Temporal performance degradation under RTN: Evaluation and mitigation for nanoscale circuits
Impact of circuit degradation on FPGA design security
Enabling quality-of-service in nanophotonic network-on-chip
MorphCache: A reconfigurable adaptive multi-level cache hierarchy
A low-power IF circuit with 5 -dB minimum input SNR for GFSK low-IF receivers
A reconfigurable computing approach for efficient and scalable parallel graph exploration
A frequent-value based PRAM memory architecture
Design implications of memristor-based RRAM cross-point structures
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