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中文摘要：
针对工艺参数变化的情况，提出一种成品率驱动的时钟偏差安排算法．提出统计时序约束图的概念，利用统计时序分析的结果将时序电路转换为统计时序约束图；将寻找关键环问题转换为最小费用／时间比值环问题，并按比例分配关键环中的时钟偏差的安全余量．实验结果表明，该算法有助于提高集成电路的成品率．
英文摘要：
A yield driven clock skew scheduling algorithm is proposed in presence of process variations. Firstly,we present the concept of statistical timing constraint graph and transform a sequential circuit into a statistical timing constraint graph by using the result of statistical timing analysis. Then, the slacks are assigned proportionally in the critical cycles, which are detected iteratively using the algorithm for minimum cost-to-time ratio cycle problem. Experimental results show that the algorithm can help with is improving the yield of integrated circuits.
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