中文摘要：

供电电压直接决定芯片性能,在IC设计的各个阶段考虑供电电压约束具有重要的意义.受制于电源线/地线（P/G）网络分析的高复杂性,尽管供电电压已成为布图规划设计中的一个设计约束,但目前在布局设计中还未考虑供电电压约束.有别于ICCG,SOR等经典的全局分析算法,提出了一种局部的连续过松弛方法（SORPECO）,并在ECO布局过程中对P/G网电压约束进行高效的分析.基于前一个布局的P/G网电压分布,针对ECO试探布局中某些轻微设计变动,SORPECO只需对这些设计变动的局部变化周边区域进行松弛,以更新P/G网电压分布.受益于P/G网络分析的局部性,SORPECO拥有局部、高效和高精度等优点.实验结果表明,与通常用于布图规划的传统高效的ICCG算法相比,SORPECO不仅精度损耗几乎可以忽略（最大误差〈0.062%）,而且可以加速2个数量级.

英文摘要：

Since supply voltage directly determines the chip performance,it is important to take the supply voltage as the design constraint at all IC design stage.Owing to the mammoth complexity of power /ground（P/G）analysis,the supply voltage has not been considered in the placement though it became a constraint of the floor-planning.Different from the traditional global analysis algorithms such as ICCG and SOR,localized successive over-relaxation method（SORPECO）is proposed in the paper.SORPECO is the first try to efficiently analyze P/G voltage distribution in ECO placements.Based on the P/G voltage distribution of previous placement solution,SORPECO can obtain a new P/G voltage distribution only through relaxing small local area surrounding some slight changes in a tentative solution.Thanks to the locality of P G network analysis,SORPECO is of advantages such as locality,efficiency,and high accuracy.In comparison with the traditional efficient ICCG algorithm usually used in floor-planning,experimental results show that SORPECO is two orders of magnitudes faster with ignored accuracy loss（maximum errors 0.062%）.