中文摘要：

主要研究时域可编程逻辑器件（FPGA）上实现低通有限冲激响应（FIR）数字滤波器结构．在分析了FIR数字滤波器的基本理论的基础上，利用Matlab设计出原型滤波器，使用全串行分布式算法作为滤波器的硬件实现算法，外围辅以单片机电路和FPGA进行通讯，并且给出了详细的算法编程和仿真波形图．突破了并行处理与流水级数的限制，可以很好地实现信号处理的实时性．同时，开发程序的可移植性好，可以缩短开发周期；数据的配置灵活，可以应用到不同的场合．

英文摘要：

The digital finite impulse response （FIR） filter in time domain is studied by using field programmed gates arrag （FPGA）. According to digital FIR filtering theory, the methods of designing FIR filter are analyzed. A scheme of hardware implementation is worked out by using distributed arithmetic algorithm. It broke out the definition of parallel process and streamline series, and can carry out the realism of signal processing. Then, the program has good replanted characteristic and can reduce developing period. It can apply to different occasions due to its flexible setting in data configuration.