中文摘要：

该文依据多级比较原理,建立了ADC功耗-速率优值模型.基于比较器数目最优算法,推导出多级ADC最优比较器数目,并提出多级ADC功耗-速率优值参数,从而得到可实现小功耗、高转换速率的多级ADC优化结构.以10位精度ADC为例,系统级仿真结果表明：多级ADC中的三级Pipelined结构可将全Flash ADC功耗降低到最小,而保持相同的转换速率;同时理论验证了以两步式结构实现多级ADC优于其他多步式结构.该优值模型可应用于高速、高精度ADC系统结构优化.

英文摘要：

Based on multi-stage comparison, a new theory incorporating Minimum Comparator Number Algorithm （MCNA） and Power-Conversion Rate Merit Model （PCRMM） is proposed, which releases the power dissipation from limitation of comparators, sub-DACs and residual amplifiers in high-speed high-resolution ADCs. Under 10-bit ADC resolution specific, theoretical analysis shows that this theory reduces the power dissipation of Flash ADC to minimum by applying 3-stage Pipelined ADC, while keeping ADC high-speed, and it also proves that two-step ADC is better than other type of multi-step ADC. This new theory can be used in designing and developing high-speed low-power ADCs.