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5Gb/s 0.18μm CMOS 半速率时钟与数据恢复电路设计
  • 期刊名称：微电子学录用
  • 时间：0
  • 相关项目：基于标准CMOS工艺的新型表面超级结射频LDMOS及其模型研究
同期刊论文项目
基于标准CMOS工艺的新型表面超级结射频LDMOS及其模型研究
期刊论文 48 会议论文 4
同项目期刊论文
A Novel RF SOI LDMOS with a Raised Drift Region
A 5-Gbit／s monolithically-integrated low-power clock recovery circuit in 0.18-μm CMOS
A High Performance Silicon-on-Insulator LDMOSTT Using Linearly Increasing Thickness Techniques
A Three-dimensional Breakdown Model of SOI Lateral Power Transistors with a Circular Layout
梯子形石墨烯纳米条带输运性质的研究
基于分组码的改进型防碰撞算法研究
Combining 2D and 3D Device Simulations for Optimizing LDMOS Design
A three dimension analytical model of surface electric field distributions for SOI lateral super jun
改进型自适应多叉树防碰撞算法研究
0.18μm CMOS集成时钟产生功能的10Gb/s复接器设计
任意纵向变掺杂横向功率器件二维耐压模型
变漂移区厚度SOI横向高压器件的优化设计
具有倾斜表面漂移区的SOI LDMOS的工艺设计
Analysis of Si3N4 Passivation effect by Self-Consistent Electro-Thermal-Mechanical Simulation in AlG
Comparison of High Voltage (200-300 Volts) Lateral Power MOSFETs for Power Integrated Circuits
Reduction of Kink Effect in SOI LDMOS Structure with Linear Drift Region Thickness
An 800 volts high voltage interconnection level shifter using floating poly field plate(FPFP) method
Multi-reversed-junction LDMOST with very high breakdown voltage per unit length
Variation of Lateral Thickness Techniques in SOI Lateral High Voltage Transistors
A 2D Analytical Model of Bulk-silicon Triple RESURF Devices
A 2.5-Gb/s fully-integrated, low-power clock and recovery circuit in 0.18-um CMOS
一种不用先验知识的单路混合信号的盲源分离新方法
一种新型的基于最大特征值的合作频谱感知算法
基于数据融合的三段式心音身份识别技术
A novel 800V multiple RESURF LDMOS utilizing linear P-top rings
Double snapback effect in LDMOS based on non-isothermal simulation
A Novel L band Satellite Beacon Receiver Based on Zero IF Converter
SOI LDMOS器件纵向耐压技术的研究进展
基于标签识别码分组的连续识别防碰撞算法研究
基于RIE技术的倾斜表面SOI功率器件制备技术
A 2.5-Gb/s fully-integrated, low-power clock and recovery circuit in 0.18-μm CMOS
A three-dimensional breakdown model of SOI lateral power transistors with a circular layout
自旋场效应晶体管的电学特性研究
石墨烯纳米条带的电子输运性质研究
准一维碳纳米管的含时输运性质的研究（英文）
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集成时钟产生功能的0．18μmCMOS10Gb／s复接器的设计
5-Gbit／s0．18-μm CMOS单片集成低功耗时钟恢复电路设计