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Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technol
ISSN号:0018-9383
期刊名称:IEEE Transactions on Electron Devices
时间:2013.11
页码:3669-3675
相关项目:新型围栅硅纳米线MOS器件的涨落性与可靠性研究
作者:
Jiang, Xiaobo|Wang, Runsheng|Yu, Tao|Chen, Jiang|Huang, Ru|
同期刊论文项目
新型围栅硅纳米线MOS器件的涨落性与可靠性研究
期刊论文 8
会议论文 20
同项目期刊论文
Two-dimensional self-limiting wet oxidation of silicon nanowires: Experiments and modeling
Study on the Ge1-xSnx/HfO2 interface and its impacts on Ge1-xSnx tunneling transistor
Experimental study on the oxide trap coupling effect in metal oxide semiconductor field effect trans
Characterization of random telegraph noise in scaled high-k/metal-gate MOSFETs with SiO2/HfO2 gate d
Impacts of short-channel effects on the random threshold voltage variation in nanoscale transistors
Design Optimization for Digital Circuits Built With Gate-All-Around Silicon Nanowire Transistors
A Comparative Study on the Impacts of Interface Traps on Tunneling FET and MOSFET