随着半导体器件特征尺寸的不断减小,传统SiO2栅介质减薄到1nm以下时会导致栅极漏电流增大、器件可靠性下降等诸多问题,已无法满足CMOS技术长远发展要求。因此,寻求替代SiO2的新型栅介质材料,减少器件的隧穿电流,提升可靠性成为CMOS技术的发展方向。如何制备化学性质稳定、性能优异的栅介质薄膜成为高k栅介质材料亟待解决的问题。论述了理想高k栅介质材料的基本要求,重点介绍了高k栅介质材料制备技术的研究进展,并分析指出了高k栅介质材料制备技术的未来发展趋势。
As the feature size of semiconductor devices continues to decrease, the thickness of the traditional Si02 gate dielectric material has gradually been thinned to 1 nm or less,leading to the increase of gate leakage current, the decline of reliability of the device and many other problems, so the SiO2 gate dielectric material can not be able to satisfy the long-term development of CMOS technology. Therefore, new alternative materials, which can reduce tunnelling current and enhance the reliability of the device, to replace SiO2 are needed to be found as the development direction of CMOS technology. How to prepare high-k gate dielectric film with stable chemical property and excellent performance is the key issue of high-k gate dielectric materials to be solved. Basic requirements for ideal high-k gate dielectric material are introduced, the research progress in high-k gate dielectric preparation techniques is highlighted, and the future development trend of high-k gate dielectric materials preparation techniques is analyzed and pointed out.