中文摘要：

文章拟在设计一个单通道微型瞬态存储测试系统，设计其整体硬件电路及CPLD内部逻辑程序，对CPLD内部逻辑电路进行仿真；传统存储测试在测试参数多、时间长、而体积小的场合因其体积较大，功耗过高而难以胜任，微型存储测试系统在传统存储测试系统的基础上对其进行单元电路的二次集成技术，主要采用CPLD代替分立元件、使用小型化封装的芯片、优化内部结构布局，使测试系统的体积大幅减小，从而提高存储测试系统抗高过载性能，增加系统使用的灵活性和通用性。

英文摘要：

We try to design a System of storage memory with one line signal import. Deign its hardware circuitry and logic program inside the complex--program--logic--device. Traditional memory--testing system could not work well in the conditions with little apace, long- testing time, more testing--parameter because of its big volume and it needs high power supply. TO design the system smaller by integrate meny chips to one chip to solve the problem that the system is not small enough that effect the testing matter. Mostly we use small chips and small chip encapsulation fashions and optimize its configuration make it come true.